Functional verification  has  become major  component  of  digital  hardware  designs.  Industry  reviews  note,  that verification often is single largest part of projects, taking more than half of overall  resources - staff, time and funds [1].   Verification of mixed-signal design and communication systems in particular, is especially difficult due to sufficient differences in design methodologies, abstraction levels and used simulation techniques.

Present paper considers applicable simulation technique for analogue high frequency circuits – Harmonic Balance (HB) and  way  to  connect  it  to  digital  subsystem  models  for  purposes  of  end-to-end  simulation  and  verification  of digital data link.

There  are  different  types  of  verification,  which  are  used  during  design  and  implementation  of  a  new  system: manufacturing verification (sample testing),  timing verification, functional verification (intention verification). The aim of  functional type of verification is to define: will system operate in accordance with specification or not.  On  that  area  of  intentions  –  analysis  of  design  and  implementation  before  they  are  created  –  is  focused functional verification.

Purpose  of  functional  verification  is  to  prove,  that  design  will  work  as  it  is  supposed.  There  are  [4]  four components to achieve that goal:

•    Define intentions
•    Define design operation
•    Compare results to be sure they coincide
•    Estimate level of confidence of verification efforts

Functional  verification  is  based  onto  possibility  to  simulate  design  under  different  stimuli,  observing  and analyzing  correctness  of  results.  Design  description  may  be  described  with  different  levels  of  details.  More abstract models describe general behavior of the system, but neglect details. Less abstract has more deal with details and closer to final implementation, but more laborious in simulation and verification.

Behavioral models are used to be considered as highest level of abstraction. The goal of that representation is to inspect  base  functionality  and,  possibly,  interaction  between  main  components.  It  is  of  importance,  that  test stimuli and system response  checks  can  be applied/performed  at  that  level,  as  it  allows  testing  of model  and testbenches. RTL represents more details of design. It is often the level, at which the most verification job is performed. 

This  level  still  can  contain  a  lot  of  software components,  but  also  requires  some  components  to simulate  parallel  nature  of  hardware.  That  is  the  reason  why  hardware  description  languages  are  used  at  this level,  such  as  Verilog  and  VHDL.  Gate-level  models  are  lowest  abstraction  level,  which  is  used  in  front-end design. At this level, all elements of logic and all interconnections are described. Despite of plethora of details, that level still represent significant abstraction, as it does not consider individual transistors.

Abovementioned  abstraction  levels  are  correct  for  digital  systems  and  can  be  considered  as  starting  point for analog and mixed-level designs, but in later case situation is different. Analog blocks, which behavior can not be described as interaction of high-level abstractions (like registers or gates), changes level hierarchy.

Traditionally, analog verification is performed bottom-up [2] and main level of description for analog device is transistor-level.  More,  behavior  and  regimes  of  the  circuit  depends  not  only  on  circuit  itself,  but  also  on environment  (load  and  stimuli  properties).  In  this  context  it  gets  important  to  be  able  to  mix  different  representation levels in one design and simulate digital subsystem at behavioral level and analog  at transistor level.

Same  time,  behavioral  representation  of  analog  blocks  looks  prospective  [5],  as  allows  significantly  decrease size of the task to be solved, saving time and resources required for verification. Behavioral models of analog blocks are similar somehow to digital one, as expresses the same level of abstraction of block functionality.

But, analog blocks has own specifics: it is necessary to consider continuous time, spectral characteristics (in case of high-frequency   blocks),   dynamic  characteristics  of  devices,  simultaneity  of  conditions;  all  that  imposes additional requirements to languages being used. VHDL-AMS [8] and Verilog-AMS [9] provide mechanisms to describe equations, which are satisfied during device or block operation. SystemC-AMS has similar properties [10].

Particular class of systems, which contains both digital and analog blocks, is communication systems. Presence of  highly  different  time  constants,  distributed  frequency-dependent  components,  high  nonlinearity  of  some devices  makes  RF  and  MW  systems  hard  to  be  simulated  by  conventional  techniques.  That  has  lead  to development  of  special  approaches  [11].  Among  most  often  used  are:  shooting  techniques,  Volterra  series techniques, HB technique and it’s derivatives.

There are three distinct requirements for analog systems representation. First one is its ability to model relevant design properties. E.g., front-end amplifier may be represented by linear models with noise, mixer will require taking  into  account  nonlinear  device  properties. 

During  power  amplifier  simulation,  accounting  of  transistor nonlinearities  can  significantly  influence  onto  properties  of  communication  link  and  has  to  be  considered  as important factor during end-to-end verification of link model.
Behavioral  representation  of  analog  blocks  allows  decreasing  task  size  while  preserving  functionality.  Thus, usage of HDLs which allow building macromodels is considered as valuable [14].

Third distinct feature is usage of VHDL-AMS or Verilog-AMS for analog part modeling. These languages are widespread  in  digital  design  and  wishes  to  follow  them  during  analog  modeling  are  natural.  However,  some additions  are  required  to  reflect  particular  features  of  analog  subsystems,  such  as  ability  to  model  frequency- dependent components [12,13].
These  three  factors:  modeling  of  relevant  properties,  ability  to  build  behavioral  analog  models  and  usage  of conventional HDLs are considered as worth of much attention in context of communication link verification.

One of means to perform simultaneous simulation of high-frequency analog and digital subsystems is called co- simulation. Technique, applied to task of  RF communication channel analysis as a part of digital communication link,  is  outlined  in  [15].    Approach  can  be  concluded  as  interchange  of  analog  and  digital  subsystems  via interfaces  during  cycle  of  (external)  digital  simulator. 

If  digital  simulator  supports  delta-cycle,  process  of solution repeats multiple times in the same moment of model time, until stable state is reached. For synchronous unidirectional blocks solution is much simpler, it is necessary to solve equations once per time step [15].

For verification, verified block is placed in testbench, as it is depicted at Fig. 1. Stimuli generator interacts with result estimation module, creating required testing sequences.

Fig. 1. Communication link verification testbench.

To  demonstrate  described  interaction  of  high-frequency  and  digital  simulation  tools,  consider  RF  amplifier simulation in the digital communication link.

Fig. 2. QPSK Link

Fig. 3. Amplifier schematic

Amplifier  is  simulated  in  Rincon  Harmonic  Balance  simulator  [16],  all  other  parts  of  link  were simulated  in Mathlab/Simulink behavioral models. Link chart is presented at Fig. 2, amplifier schematic - at Fig. 3, simulated in-phase and quadrature components are presented at Fig. 4.

Analysis  of  task  of  digital  communication  link  verification  is  performed,  related  problems  are  outlined  and possibility  to  use  Modulation  HB  along  with  synchronous  digital  model  for  complete  communication  link simulation is demonstrated.

Example of simulation of one-stage amplifier in digital channel is provides, results of simulation are presented.

Fig. 4. Normalized inphase and quadrature components before and after amplifier, time is in ms.